1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a dynamic random access memory having memory cells each of which has a single transistor and a single capacitive element.
2. Description of the Related Art
With the increasing needs for high performance of digital systems, the current development thrust of random access memories (referred to as "DRAMs" hereinafter) is toward dramatic density improvement. The improvement of the integration density of DRAMs will require decrease in the size of each memory cell of the DRAMs. The manufacture of miniaturized memory cells has been significantly improved recently in large part of role played by advanced micro-fabrication technology.
Unfortunately, in presently available DRAMs, a coupling capacitance which is inherently present between neighboring data transfer lines arranged in the planar matrix of memory cells, increases in accordance with increase in the integration density of memory cells in the DRAMs. The presence of the increased coupling capacitance strengthens the intensity of interference noise produced by a data transfer line adjacent to a data line being subjected to data reading and applied onto the data reading line. Such undesirable phenomenon have been reported in many research papers. For example, according to Papers of International Solid State Circuits Committee (ISSCC) Feb. 19, 1988 at pages 250, 251, 391 and 392, it has been demonstrated that the noise interference between internal data lines called "bit lines" tends to be increased not only when a cell storage data is being read onto the corresponding bit line, but also when the read data is being sensed and amplified by a sense amplifier circuit.
A significant disadvantage of the conventional DRAM is that the interference noise between the neighboring bit lines undesirably increases the time required for cell data amplification in a selected bit line, and the necessary sensing time becomes longer. This results in the high-speed data accessing being damaged seriously in the DRAM. In the worst case, the potential difference between a read data voltage and a corresponding dummy cell voltage to be input to the sense amplifier decreases below the minimum level of voltage that can be sensed by the sense amplifier. This leads to an accidental malfunction that the sense amplifier latches the memory cell data input thereto. The DRAM is unreliable in that many sense amplifiers arranged in bit line pairs may experience serious misjudgment on logical level of the read data, generating bit reading errors in the memory.